1. Field of the Invention
The present invention pertains to memories and memory testing. More particularly, this invention relates to electrical testing of embedded memories.
2. Background
Continual advances in processor technology have led to continual increases in the functionality provided in a single processor chip. One example of such functionality is on-chip memories, often referred to as cache memories. On-chip cache memories provide storage of data and/or instructions as well as various other control and/or address information for use by the execution unit(s) and other internal logic of the processor. These on-chip cache memories are typically very fast memories, with the combination of their speed as well as their close physical locality to the execution unit(s) and other internal logic leading to fast memory accesses for the information stored in these memories.
However, the fabrication of memories does not produce perfect results and, therefore, processors will occasionally be fabricated which have faulty memories. The faults may be complete failure of the memory cells, failure of particular cells, failure of connections between cells, failures of sensing circuits, etc. Therefore, given that processors with such faulty memories may be fabricated, it would be beneficial to provide a way to test the electrical characteristics of the embedded memories to verify their performance (e.g., to determine whether there are any electrical faults within the cells of the embedded memory).
Unfortunately, given the embedded nature of these on-chip memories, it is typically not possible to directly and easily access the inputs and outputs of particular memory cells or sense amplifiers, thereby making testing of the electrical characteristics of the circuits extremely difficult. Thus, analysis of the faulty part of the embedded memory array is difficult to do.
Thus, a need exists for improved testing of embedded memories. The present invention allows for the analysis of known faulty memory cells, bit lines and/or sense amplifiers as detected by traditional memory tests, and/or analysis of intrinsic behavior or electrical characteristics.
A method and apparatus for electrical testing of embedded memory is described herein. According to one aspect of the present invention, a processor includes a plurality of I/O connectors and an embedded memory array having a plurality of memory cells and a plurality of bitlines coupled to the plurality of memory cells. The processor also includes low yield analysis circuitry, coupled to both the embedded memory array and a first connector of the plurality of I/O connectors, to provide a coupling between a portion of the embedded memory array and the first connector.
According to one aspect of the present invention, a method, in a processor, includes receiving a low yield analysis control command and control command parameters from a source external to the processor. Low yield analysis circuitry within the processor is enabled, and a first signal is asserted, based on the control command parameters, to a plurality of multiplexers of the low yield analysis circuitry to couple a first set of inputs to the plurality of multiplexers to the outputs of the plurality of multiplexers. A second signal is asserted, based on the control command parameters, to a plurality of transmission gates to enable a selected one of the plurality of transmission gates to couple the output of one of the plurality of multiplexers to an I/O connector.